struct nand_sdr_timings — SDR NAND chip timings
struct nand_sdr_timings { u32 tALH_min; u32 tADL_min; u32 tALS_min; u32 tAR_min; u32 tCEA_max; u32 tCH_min; u32 tCHZ_max; u32 tCLH_min; u32 tCLR_min; u32 tCLS_min; u32 tCOH_min; u32 tCS_min; u32 tDH_min; u32 tDS_min; u32 tFEAT_max; u32 tIR_min; u32 tITC_max; u32 tRC_min; u32 tREA_max; u32 tREH_min; u32 tRHOH_min; u32 tRHW_min; u32 tRHZ_max; u32 tRLOH_min; u32 tRP_min; u32 tRR_min; u64 tRST_max; u32 tWB_max; u32 tWC_min; u32 tWH_min; u32 tWHR_min; u32 tWP_min; u32 tWW_min; };
ALE hold time
ALE to data loading time
ALE setup time
ALE to RE# delay
CE# access time
CE# hold time
CE# high to output hi-Z
CLE hold time
CLE to RE# delay
CLE setup time
CE# high to output hold
CE# setup time
Data hold time
Data setup time
Busy time for Set Features and Get Features
Output hi-Z to RE# low
Interface and Timing Mode Change time
RE# cycle time
RE# access time
RE# high hold time
RE# high to output hold
RE# high to WE# low
RE# high to output hi-Z
RE# low to output hold
RE# pulse width
Ready to RE# low (data only)
Device reset time, measured from the falling edge of R/B# to the rising edge of R/B#.
WE# high to SR[6] low
WE# cycle time
WE# high hold time
WE# high to RE# low
WE# pulse width
WP# transition to WE# low
This struct defines the timing requirements of a SDR NAND chip. These information can be found in every NAND datasheets and the timings meaning are described in the ONFI specifications: www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing Parameters)
All these timings are expressed in picoseconds.